Voltage controlled oscillators (VCOs) are very useful components for a wide variety of integrated circuit applications. Voltage controlled oscillators (VCO) may be implemented using a parallel combination of a passive inductance (L) and a passive capacitance (C). The voltage and current for an inductor are related as V=L di/dt. For a capacitor, the relationship of current and voltage is i=C dV/dt or V=1/C∫i dt. Applying Kirchoff's voltage law for the parallel combination of an inductor and capacitor, L di/dt=1/C∫i dt. The relationship of voltage and current between the parallel inductor and capacitor may be rearranged and differentiated such that L d2i/d2t−1/C i. A solution to this equation is i=i0 sin ωt, where ω=1/√LC. Thus, a sinusoidal timing signal may be generated by the VCO at an operating frequency of f=½π1/√LC.
Thus far, LC VCOs have been limited to wirebond designs. Flip chip designs, which use conductive bumps to make electrical connections, offer smaller sizes, improved performance, and lower cost, as well as flexibility and reliability, when compared to wirebond. The use of an LC VCO in a silicon flip chip design is hampered by the need to synthesize the L with a spiral inductor and the lack of tunability. VCO configurations with spiral inductors consume a large amount of silicon area, can have poor performance when used in flip chip applications, have a low quality factor, and may interact with adjacent metal layers and flip chip underfill material. Wirebond is not suitable for high speed, high density IO that are commonly found on Application Specific Integrated Circuits (ASICs).
Therefore, it would be desirable to reduce the size of a voltage controlled oscillator by replacing the passive inductor with an active inductor.